/* quiccIntrCtl.c - Motorola MPC 83XX interrupt controller driver */

/* Copyright 1984-2005 Wind River Systems, Inc. */
#include "copyright_wrs.h"

/*
modification history
--------------------
01a,10jan05,dtr  adapted from m8260IntrCtl.
*/

/*
DESCRIPTION
The PowerPC 83XX CPU is divided in three units: PowerPC core, System
Interface Unit (SIU) and Communication Engine (CE). The PowerPC
core accepts only one external interrupt exception (vector 0x500). The SIU
provides an interrupt controller which provides 92 interrupt sources
The Interrupt controller is connected to the PowerPC core external 
interrupt. This library provides the routines to manage this interrupt 
controllers.

quiccIntrInit() connects the default demultiplexer, quiccIntrDeMux(), to the 
external interrupt vector and initializes a table containing a function pointer
and an associated parameter for each interrupt source. quiccIntrInit() is called
by sysHwInit() from sysLib.c.

The default demultimplexer, quiccIntrDeMux() detects which peripheral or 
controller has raised an interrupt and calls the associated routine with its 
parameter. 

INCLUDE FILES: quiccIntrCtl.h
*/

/* includes */

#include "intLib.h"
#include "iv.h"
#include "quiccIntrCtl.h"

#ifdef  INCLUDE_WINDVIEW
#include "private/funcBindP.h"
#include "private/eventP.h"
#endif /* INCLUDE_WINDVIEW */

/* local */

INTR_HANDLER  intrVecTable[IVEC_MAX+1];   /*  Intr vector table */

/* SIU Interrupt Mask structure; a value for the high and low parts */
typedef struct siu_int_mask
    {
    UINT32  simr_h;
    UINT32  simr_l;
    UINT32  semr;
    } SIU_INT_MASK;

/* 
 * for a give inum, return a pair of masks, one for SIMR_H and one for SIMR_L,
 * which will enable only higher priority interrupts.
 */

LOCAL SIU_INT_MASK enableHighPriInts[] =
    {
    {0x00000000, 0x00000000, 0x00000000},   /* interrupt 0 error - enable nothing */
    {0xFF000020, 0x30000000, 0x00000000},         /* PCIE */
    {0x00000000, 0x00000000, 0x00000000},         /* Reserved */
    {0x00000000, 0x00000000, 0x00000000},         /* Reserved */
    {0x00000000, 0x00000000, 0x00000000},         /* Reserved */
    {0x00000000, 0x00000000, 0x00000000},         /* Reserved */
    {0x00000000, 0x00000000, 0x00000000},         /* Reserved */
    {0x00000000, 0x00000000, 0x00000000},         /* Reserved */
    {0x00000000, 0x00000000, 0x00000000},         /* Reserved */
    {0x00000000, 0x00000000, 0x00000000},         /* Reserved */
    {0xFF000020, 0x30000000, 0x00000000},         /* UART1 */
    {0xFF000020, 0x30000000, 0x00000000},         /* UART2 */
    {0xFF000000, 0x00000000, 0x00000000},         /* SEC   */
    {0x00000000, 0x00000000, 0x00000000},         /* Reserved */
    {0x00000000, 0x00000000, 0x00000000},         /* Reserved */
    {0xFF000020, 0x30000000, 0x00000000},         /* I2C1 */
    {0xFF000020, 0x30000000, 0x00000000},         /* I2C2 */
    {0xFF000020, 0x30000000, 0x00000000},         /* SPI */
    {0xFF000020, 0x30000000, 0x00000000},         /* IRQ1 */
    {0xFF000020, 0x30000000, 0x00000000},         /* IRQ2 */
    {0xFF000020, 0x30000000, 0x00000000},         /* IRQ3 */
    {0xFF000020, 0x30000000, 0x00000000},         /* IRQ4 */
    {0xFF000020, 0x30000000, 0x00000000},         /* IRQ5 */
    {0xFF000020, 0x30000000, 0x00000000},         /* IRQ6 */
    {0xFF000020, 0x30000000, 0x00000000},         /* IRQ7 **23**/
    {0x00000000, 0x00000000, 0x00000000},         /* Reserved */
    {0x00000000, 0x00000000, 0x00000000},         /* Reserved */
    {0x00000000, 0x00000000, 0x00000000},         /* Reserved */
    {0x00000000, 0x00000000, 0x00000000},         /* Reserved */
    {0x00000000, 0x00000000, 0x00000000},         /* Reserved */
    {0x00000000, 0x00000000, 0x00000000},         /* Reserved */
    {0x00000000, 0x00000000, 0x00000000},         /* Reserved */
    {0x00000000, 0x00000000, 0x00000000},         /* Reserved */
    {0x00000000, 0x00000000, 0x00000000},         /* TSEC1 Tx */
    {0x00000000, 0x00000000, 0x00000000},         /* TSEC1 Rx */
    {0x00000000, 0x00000000, 0x00000000},         /* TSEC1 Err */
    {0x00000000, 0x00000000, 0x00000000},         /* TSEC2 Tx */
    {0x00000000, 0x00000000, 0x00000000},         /* TSEC2 Rx */
    {0x00000000, 0x00000000, 0x00000000},         /* TSEC2 Err */
    {0xFF000020, 0x30000000, 0x00000000},         /* USB2 DR */
    {0xFF000020, 0x30000000, 0x00000000},         /* USB2 MPH */
    {0x00000000, 0x00000000, 0x00000000},         /* Reserved */
    {0x00000000, 0x00000000, 0x00000000},         /* Reserved */
    {0x00000000, 0x00000000, 0x00000000},         /* Reserved */
    {0x00000000, 0x00000000, 0x00000000},         /* Reserved */
    {0x00000000, 0x00000000, 0x00000000},         /* Reserved */
    {0x00000000, 0x00000000, 0x00000000},         /* Reserved */
    {0x00000000, 0x00000000, 0x00000000},         /* Reserved */
    {0x00000000, 0x00000000, 0x00000000},         /* Reserved  add by chengxiang */    
    {0x00000000, 0x00000000, 0x00000000},         /* IRQ0 ***48**/
    {0x00000000, 0x00000000, 0x00000000},         /* Reserved */
    {0x00000000, 0x00000000, 0x00000000},         /* Reserved 50*/
    {0x00000000, 0x00000000, 0x00000000},         /* Reserved */
    {0x00000000, 0x00000000, 0x00000000},         /* Reserved */
    {0x00000000, 0x00000000, 0x00000000},         /* Reserved */
    {0x00000000, 0x00000000, 0x00000000},         /* Reserved */
    {0x00000000, 0x00000000, 0x00000000},         /* Reserved */
    {0x00000000, 0x00000000, 0x00000000},         /* Reserved */
    {0x00000000, 0x00000000, 0x00000000},         /* Reserved */
    {0x00000000, 0x00000000, 0x00000000},         /* Reserved */
    {0x00000000, 0x00000000, 0x00000000},         /* Reserved */
    {0x00000000, 0x00000000, 0x00000000},         /* Reserved  60*/
    {0x00000000, 0x00000000, 0x00000000},         /* Reserved */
    {0x00000000, 0x00000000, 0x00000000},         /* Reserved */
    {0x00000000, 0x00000000, 0x00000000},         /* Reserved */
    {0xFF000020, 0x30000000, 0x00000000},         /* RTC SEC 64*/
    {0xFF000020, 0x30000000, 0x00000000},         /* PIT */
    {0xFF000020, 0x00000000, 0x00000000},         /* PCI1  66*/
    {0xFF000020, 0x00000000, 0x00000000},         /* PCI2 */
    {0xFF000020, 0x30000000, 0x00000000},         /* RTC ALR */
    {0xFF000020, 0x30000000, 0x00000000},         /* MU */
    {0xFF000020, 0x30000000, 0x00000000},         /* SBA */
    {0xFF000020, 0x30000000, 0x00000000},         /* DMA */
    {0xFF000020, 0x30000000, 0x00000000},         /* GTM4 */
    {0xFF000020, 0x30000000, 0x00000000},         /* GTM8 */
    {0xFF000020, 0x30000000, 0x00000000},         /* CPIO1 */
    {0xFF000020, 0x30000000, 0x00000000},         /* GPIO2 */
    {0xFF000020, 0x30000000, 0x00000000},         /* DDR */
    {0xFF000020, 0x30000000, 0x00000000},         /* LBC */
    {0xFF000020, 0x30000000, 0x00000000},         /* GTM2 */
    {0xFF000020, 0x30000000, 0x00000000},         /* GTM6 */
    {0xFF000020, 0x30000000, 0x00000000},         /* PMC */
    {0x00000000, 0x00000000, 0x00000000},         /* Reserved */
    {0x00000000, 0x00000000, 0x00000000},         /* Reserved */
    {0x00000000, 0x00000000, 0x00000000},         /* Reserved */
    {0xFF000020, 0x30000000, 0x00000000},         /* GTM3 */
    {0xFF000020, 0x30000000, 0x00000000},         /* GTM7 */
    {0x00000000, 0x00000000, 0x00000000},         /* Reserved */
    {0x00000000, 0x00000000, 0x00000000},         /* Reserved */
    {0x00000000, 0x00000000, 0x00000000},         /* Reserved */
    {0x00000000, 0x00000000, 0x00000000},         /* Reserved */
    {0xFF000020, 0x30000000, 0x00000000},         /* GTM1 */
    {0xFF000020, 0x30000000, 0x00000000},         /* GTM5 */
    {0x00000000, 0x00000000, 0x00000000},         /* Reserved */
    {0x00000000, 0x00000000, 0x00000000},         /* Reserved */
    {0x00000000, 0x00000000, 0x00000000},         /* Reserved */
    {0x00000000, 0x00000000, 0x00000000},         /* Reserved */
    {0x00000000, 0x00000000, 0x00000000},         /* Reserved */
    {0x00000000, 0x00000000, 0x00000000},         /* Reserved */
    {0x00000000, 0x00000000, 0x00000000},         /* Reserved */
    {0x00000000, 0x00000000, 0x00000000},         /* Reserved */
    {0x00000000, 0x00000000, 0x00000000},         /* Reserved */
    {0x00000000, 0x00000000, 0x00000000},         /* Reserved */
    {0x00000000, 0x00000000, 0x00000000},         /* Reserved */
    {0x00000000, 0x00000000, 0x00000000},         /* Reserved */
    {0x00000000, 0x00000000, 0x00000000},         /* Reserved */
    {0x00000000, 0x00000000, 0x00000000},         /* Reserved */
    {0x00000000, 0x00000000, 0x00000000},         /* Reserved */
    {0x00000000, 0x00000000, 0x00000000},         /* Reserved */
    {0x00000000, 0x00000000, 0x00000000},         /* Reserved */
    {0x00000000, 0x00000000, 0x00000000},         /* Reserved */
    {0x00000000, 0x00000000, 0x00000000},         /* Reserved */
    {0x00000000, 0x00000000, 0x00000000},         /* Reserved */
    {0x00000000, 0x00000000, 0x00000000},         /* Reserved */
    {0x00000000, 0x00000000, 0x00000000},         /* Reserved */
    {0x00000000, 0x00000000, 0x00000000},         /* Reserved */
    {0x00000000, 0x00000000, 0x00000000},         /* Reserved */
    {0x00000000, 0x00000000, 0x00000000},         /* Reserved */
    {0x00000000, 0x00000000, 0x00000000},         /* Reserved */
    {0x00000000, 0x00000000, 0x00000000},         /* Reserved */
    {0x00000000, 0x00000000, 0x00000000},         /* Reserved */
    {0x00000000, 0x00000000, 0x00000000},         /* Reserved */
    {0x00000000, 0x00000000, 0x00000000},         /* Reserved */
    {0x00000000, 0x00000000, 0x00000000},         /* Reserved */
    {0x00000000, 0x00000000, 0x00000000},         /* Reserved */
    {0x00000000, 0x00000000, 0x00000000},         /* Reserved */
    {0x00000000, 0x00000000, 0x00000000},         /* Reserved */
    {0x00000000, 0x00000000, 0x00000000},         /* Reserved */
    {0x00000000, 0x00000000, 0x00000000}          /* Reserved */
    };



LOCAL UINT32        iNumToMaskPattern[] = 
    {
    0x00000000,         /* interrupt number 0: Error */
    0x00008000,         /* PCIE */
    0x00000000,         /* Reserved */
    0x00000000,         /* Reserved */
    0x00000000,         /* Reserved */
    0x00000000,         /* Reserved */
    0x00000000,         /* Reserved */
    0x00000000,         /* Reserved */
    0x00000000,         /* Reserved */
    0x00000080,         /* UART1  9*/
    0x00000040,         /* UART2   10*/
    0x00000020,         /* SEC   */
    0x00000000,         /* Reserved */
    0x00000000,         /* Reserved */
    0x00000004,         /* I2C1 */
    0x00000002,         /* I2C2 */
    0x00000001,         /* SPI */
    0x40000000,         /* IRQ1   17*/
    0x20000000,         /* IRQ2 */
    0x10000000,         /* IRQ3 */
    0x08000000,         /* IRQ4 */
    0x04000000,         /* IRQ5 */
    0x02000000,         /* IRQ6 */
    0x01000000,         /* IRQ7 **23**/
    0x00000000,         /* Reserved */
    0x00000000,         /* Reserved */
    0x00000000,         /* Reserved */
    0x00000000,         /* Reserved */
    0x00000000,         /* Reserved */
    0x00000000,         /* Reserved */
    0x00000000,         /* Reserved */
    0x00000000,         /* Reserved */
    0x80000000,         /* TSEC1 Tx */
    0x40000000,         /* TSEC1 Rx */
    0x20000000,         /* TSEC1 Err */
    0x10000000,         /* TSEC2 Tx */
    0x08000000,         /* TSEC2 Rx */
    0x04000000,         /* TSEC2 Err */
    0x02000000,         /* USB2 DR */
    0x01000000,         /* USB2 MPH */
    0x00000000,         /* Reserved */
    0x00000000,         /* Reserved */
    0x00000000,         /* Reserved */
    0x00000000,         /* Reserved */
    0x00000000,         /* Reserved */
    0x00000000,         /* Reserved */
    0x00000000,         /* Reserved */
     0x00000000,         /* Reserved */
    0x80000000,         /* IRQ0 ***48**/
    0x00000000,         /* Reserved */
    0x00000000,         /* Reserved  50*/
    0x00000000,         /* Reserved */
    0x00000000,         /* Reserved */
    0x00000000,         /* Reserved */
    0x00000000,         /* Reserved */
    0x00000000,         /* Reserved */
    0x00000000,         /* Reserved */
    0x00000000,         /* Reserved */
    0x00000000,         /* Reserved */
    0x00000000,         /* Reserved */
    0x00000000,         /* Reserved 60*/
    0x00000000,         /* Reserved */
    0x00000000,         /* Reserved */
    0x00000000,         /* Reserved */
    0x80000000,         /* RTC SEC  64*/
    0x40000000,         /* PIT */
    0x20000000,         /* PCI1 */
    0x10000000,         /* PCI2 */
    0x08000000,         /* RTC ALR */
    0x04000000,         /* MU */
    0x02000000,         /* SBA  70*/
    0x01000000,         /* DMA */
    0x00800000,         /* GTM4 */
    0x00400000,         /* GTM8 */
    0x00200000,         /* CPIO1 */
    0x00100000,         /* GPIO2 */
    0x00080000,         /* DDR */
    0x00040000,         /* LBC */
    0x00020000,         /* GTM2 */
    0x00010000,         /* GTM6 */
    0x00008000,         /* PMC */
    0x00000000,         /* Reserved */
    0x00000000,         /* Reserved */
    0x00000000,         /* Reserved */
    0x00000800,         /* GTM3 */
    0x00000400,         /* GTM7 */
    0x00000000,         /* Reserved */
    0x00000000,         /* Reserved */
    0x00000000,         /* Reserved */
    0x00000000,         /* Reserved */
    0x00000040,         /* GTM1 */
    0x00000020,         /* GTM5 */
    0x00000000,         /* Reserved */
    0x00000000,         /* Reserved */
    0x00000000,         /* Reserved */
    0x00000000,         /* Reserved */
    0x00000000,         /* Reserved */
    0x00000000,         /* Reserved */
    0x00000000,         /* Reserved */
    0x00000000,         /* Reserved */
    0x00000000,         /* Reserved */
    0x00000000,         /* Reserved */
    0x00000000,         /* Reserved */
    0x00000000,         /* Reserved */
    0x00000000,         /* Reserved */
    0x00000000,         /* Reserved */
    0x00000000,         /* Reserved */
    0x00000000,         /* Reserved */
    0x00000000,         /* Reserved */
    0x00000000,         /* Reserved */
    0x00000000,         /* Reserved */
    0x00000000,         /* Reserved */
    0x00000000,         /* Reserved */
    0x00000000,         /* Reserved */
    0x00000000,         /* Reserved */
    0x00000000,         /* Reserved */
    0x00000000,         /* Reserved */
    0x00000000,         /* Reserved */
    0x00000000,         /* Reserved */
    0x00000000,         /* Reserved */
    0x00000000,         /* Reserved */
    0x00000000,         /* Reserved */
    0x00000000,         /* Reserved */
    0x00000000,         /* Reserved */
    0x00000000,         /* Reserved */
    0x00000000,         /* Reserved */
    0x00000000,         /* Reserved */
    0x00000000          /* Reserved */
    };

/* forward declarations */

LOCAL void  quiccIntrDeMux (void);
LOCAL STATUS    quiccIntConnect (VOIDFUNCPTR *, VOIDFUNCPTR, int);
VOIDFUNCPTR defaultVec;         /* INTR3 default vector */

void defaultISR(int vector)
    {
    logMsg("Spurious interrupt 0x%x\n",vector,0,0,0,0,0);
    }

/**************************************************************************
*
* quiccIntrInit - initialize the interrupt manager for the PowerPC 83XX
*
* This routine connects the default demultiplexer, quiccIntrDeMux(), to the 
* external interrupt vector and associates all 
* interrupt sources with the default interrupt handler.  This routine is
* called by sysHwInit() in sysLib.c.
*
* NOTE: All interrupt from the SIU unit are enabled, CICR is setup so
* that SCC1 has the highest relative interrupt priority, through SCC4 with the
* lowest.
*
* RETURN : OK always
*/

STATUS quiccIntrInit 
    (
    )
    {
    int     vector;

    /* Get the default vector connected to the External Interrupt (0x500) */

    defaultVec = defaultISR;

    /* Connect the interrupt demultiplexer to External Interrupt (0x500) */

    excIntConnect ((VOIDFUNCPTR *) _EXC_OFF_INTR, quiccIntrDeMux);

    /* Install `system' intConnect routine */

    if (_func_intConnectRtn == NULL)
        _func_intConnectRtn = quiccIntConnect;

    if (_func_intEnableRtn == NULL)
        _func_intEnableRtn = quiccIntEnable;

    if (_func_intDisableRtn == NULL)
        _func_intDisableRtn = quiccIntDisable;

    /* Set all vectors to default handler */

    memset (intrVecTable,0,(sizeof(INTR_HANDLER) * (IVEC_MAX + 1)));

    for (vector = 0; vector <= IVEC_MAX; vector++)
	intConnect (INUM_TO_IVEC(vector), (VOIDFUNCPTR) defaultVec, vector); 


    /* disable all interrupts */
    *QUICC_SIMR_L(CCSBAR) = 0x00000000;
    *QUICC_SIMR_H(CCSBAR) = 0x00000000;
    *QUICC_SEMSR(CCSBAR) = 0x00000000;

    return (OK);
 
    }

/***********
* quiccIntConnect - connect a routine to an interrupt 
*
* This routine connects any C or assembly routine to one of the multiple 
* sources of interrupts.
*
* The connected routine can be any normal C code, except that it must not 
* invoke certain operating system functions that may block or perform I/O
* operations.
*
* <vector> types are defined in h/drv/intrClt/quiccIntr.h.
*
* RETURNS: OK, or ERROR if <vector> is unknown.
*
* SEE ALSO: quiccIntr.h***************************************************************

*/

LOCAL STATUS quiccIntConnect
    (
    VOIDFUNCPTR *   vector,     /* interrupt vector to attach to */
    VOIDFUNCPTR     routine,    /* routine to be called */
    int         parameter   /* parameter to be passed to routine */
    )
    {

    /* test the vector */

    if ((int)(vector) > IVEC_MAX)
	return (ERROR);

    if ((intrVecTable[(int)(vector)].vec == defaultVec) || (intrVecTable[(int)(vector)].vec == NULL)) 
	{
	intrVecTable[(int)(vector)].vec = routine;
	intrVecTable[(int)(vector)].arg = parameter;
	}
    else
	{
	if(intrVecTable[(int)(vector)].pNext!=NULL)
	    {
	    INTR_HANDLER *temp1Next,*temp2Next;

	    temp2Next = (INTR_HANDLER*)intrVecTable[(int)(vector)].pNext;
	    temp1Next = (INTR_HANDLER*)intrVecTable[(int)(vector)].pNext;
	    
	    while(temp1Next !=NULL)
		{
		temp2Next = temp1Next;
		temp1Next = (INTR_HANDLER*)temp2Next->pNext;
		}

	    temp2Next->pNext = (void*)malloc (sizeof(INTR_HANDLER));
	    ((INTR_HANDLER*)temp2Next->pNext)->vec = routine;
	    ((INTR_HANDLER*)temp2Next->pNext)->arg = parameter;
	    }
	}

    return (OK);
    }

/**************************************************************************
*
* quiccIntrDeMux - SIU interrupt demultiplexer 
*
* This routine must be bound to external interrupt exception (vector 0x500). 
* It is used to call the appropriate handler with its argument when an
* interrupt occurs. 
*
* The interrupts are prioritized in the following order:
*
* NOTE: when this function is called the interrupts are still locked. It's
* this function responsability to unlock the interrupt.
*
* RETURNS: N/A
*/

LOCAL void quiccIntrDeMux (void)
    {
    VINT32  intVec;         /* interrupt vector */
    UINT32  oldIntMask_L;       /* current interrupt mask */
    UINT32  oldIntMask_H;       /* current interrupt mask */
    UINT32  oldIntMask_E;       /* current interrupt mask */
    UINT32  intLevel = _PPC_MSR_EE;

    /* read the interrupt vector register */

    intVec = (0x0000007f & (*QUICC_SIVEC(CCSBAR)));

#ifdef  INCLUDE_WINDVIEW
    WV_EVT_INT_ENT(intVec)
#endif /* INCLUDE_WINDVIEW */

    if ( intVec != 0 )
        {
        /* save the current interrupt mask */ 

        oldIntMask_L = * QUICC_SIMR_L(CCSBAR);
        oldIntMask_H = * QUICC_SIMR_H(CCSBAR);
        oldIntMask_E = * QUICC_SEMSR(CCSBAR);       

        /* enable only the higher priority interrupts */

        * QUICC_SIMR_L(CCSBAR)&= 
        enableHighPriInts[QUICC_IVEC_TO_INUM((VOIDFUNCPTR *)intVec)].simr_l;
        * QUICC_SIMR_H(CCSBAR)&= 
        enableHighPriInts[QUICC_IVEC_TO_INUM((VOIDFUNCPTR *)intVec)].simr_h;
        * QUICC_SEMSR(CCSBAR)&= 
        enableHighPriInts[QUICC_IVEC_TO_INUM((VOIDFUNCPTR *)intVec)].semr;

	intUnlock (_PPC_MSR_EE);

	/* call the Interrupt Handler */

        /* table is indexed by vector */
	
	intrVecTable[intVec].vec (intrVecTable[intVec].arg); 

	if(intrVecTable[intVec].pNext !=NULL)
	    {
	    INTR_HANDLER *pNext;
	    pNext = (INTR_HANDLER*)intrVecTable[intVec].pNext;
	    while (pNext !=NULL)
		{
		pNext->vec (pNext->arg);
		pNext = (INTR_HANDLER*)pNext->pNext;
		}
	    }

	if ( ((intVec >= 17) && (intVec <= 23)) || (intVec == 48) )
	    {
	    *QUICC_SEPNR(CCSBAR) = iNumToMaskPattern[intVec] ;
	    }

	/* restore the interrupt mask */
	intLevel = intLock ();

        * QUICC_SIMR_L(CCSBAR) = oldIntMask_L;
        * QUICC_SIMR_H(CCSBAR) = oldIntMask_H;
        * QUICC_SEMSR(CCSBAR) = oldIntMask_E;

        intUnlock (intLevel);

        }

    return;
    }

/************************************************************************
*
* quiccIntEnable - enable the indicated interrupt
*
* This routine will enable the indicated interrupt by setting the appropriate
* bit in the SIU Interrupt Mask Registers.
*
* The design of the 83XX presents the following design requirements:
*
* 1. the mapping from interrupt number to mask bit can not be represented by 
*    a function. An array, indexed by interrupt number (INUM), is used to map
*    the interrupt number to the appropriate mask. 
*
* 2. There are two 32 bit mask registers (SIMR_L and SIMR_H). The interrupt
*    number must be compared to 4 ranges to determine which register contains
*    its mask bit:
*   
* .CS
*   interrupt number
*   in quiccIntrCtl.h       register
*   ----------------        -------
*   0-15                    SIMR_L
*   16-31                   SIMR_H
*   32-47                   SIMR_L
*   48-63                   SIMR_H
* .CE
*
* RETURNS: 0, always.
*/

int quiccIntEnable 
    (
    int intNum      /* interrupt level to enable */
    )
    {
    if ((intNum >= 0) && (intNum <= IVEC_MAX))
        {
	if ((intNum >= 64) && (intNum <= 128))
	    *QUICC_SIMR_L(CCSBAR) |= iNumToMaskPattern[intNum];   
	else
	    {
	    if ( ((intNum>=17) && (intNum<=31)) || (intNum == 48))
		{
		/* Use as external Mask */
		*QUICC_SEMSR(CCSBAR)  |= iNumToMaskPattern[intNum];
		}
	    else
		{
		*QUICC_SIMR_H(CCSBAR) |= iNumToMaskPattern[intNum];
		}
	    }
        }

    return 0;
    }

/**************************************************************************
*
* quiccIntDisable - Disable one of the Level or IRQ interrupts into the SIU
*
* This routine will mask the bit in the SIMASK register corresponding to
* the requested interrupt level.  
* 
* RETURNS: 0, always.
*/

int quiccIntDisable
    (
    int intNum          /* interrupt level to disable */
    )
    {
    if ((intNum >= 0) && (intNum <= IVEC_MAX))
        {
	if ((intNum >= 64) && (intNum <= 128))
	    *QUICC_SIMR_L(CCSBAR) &= ~iNumToMaskPattern[intNum];   
	else
	    {
	    if( ((intNum>=17) && (intNum<=31)) || (intNum == 48))
		{
		/* Use as external Mask */
		*QUICC_SEMSR(CCSBAR) &= ~iNumToMaskPattern[intNum];
		}
	    else
		{
		*QUICC_SIMR_H(CCSBAR) &= ~iNumToMaskPattern[intNum];
		}
	    }
        }

    return 0;
    }

VOIDFUNCPTR * quiccInumToIvec 
    (
    int intNum
    )
    {

    return ((VOIDFUNCPTR *) intNum);
    }

VOIDFUNCPTR * m8260InumToIvec 
    (
    int intNum
    )
    {
		return quiccInumToIvec(intNum);
}
/**************************************************************************
*
* quiccIvecToInum - get the relevant interrupt number
*
* This routine finds out the interrupt number associated with the vector
* in <vector>.
*
* <vector> types are defined in h/drv/intrClt/quiccIntr.h.
*
* RETURNS: the interrupt number for the vector
*
* SEE ALSO: quiccIntr.h
*/
 
int quiccIvecToInum
    (
    VOIDFUNCPTR *       vector         /* interrupt vector to attach to */
    )
    {
 
    /* test the vector */
 
    return ((int) vector);
    }

